The presently disclosed embodiments deal with pixel arrays, and more particularly, to mismatch suppression and offset cancellation of components within the pixel arrays and readout circuits.
Electronic devices and components have found numerous applications in chemistry and biology (more generally, “life sciences”), especially for detection and measurement of various chemical and biological reactions and identification, detection and measurement of various compounds. One such electronic device is referred to as an ion-sensitive field effect transistor, often denoted in the relevant literature as an “ISFET” (or pHFET). ISFETs conventionally have been explored, primarily in the academic and research community, to facilitate measurement of the hydrogen ion concentration of a solution (commonly denoted as “pH”). An ISFET is referred to, more generally, as a chemically-sensitive sensor herein.
More specifically, an ISFET is an impedance transformation device that operates in a manner similar to that of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and is particularly configured to selectively measure ion activity in a solution (e.g., hydrogen ions in the solution are the “analytes”). A detailed theory of operation of an ISFET is given in “Thirty years of ISFETOLOGY: what happened in the past 30 years and what may happen in the next 30 years,” P. Bergveld, Sens. Actuators, 88 (2003), pp. 1-20 (“Bergveld”), which publication is hereby incorporated herein by reference in its entirety.
Details of fabricating an ISFET using a conventional CMOS (Complementary Metal Oxide Semiconductor) process may be found in Rothberg, et al., U.S. Patent Publication No. 2010/0301398, Rothberg, et al., U.S. Patent Publication No. 2010/0282617, and Rothberg et al, U.S. Patent Publication 2009/0026082; these patent publications are collectively referred to as “Rothberg”, and are all incorporated herein by reference in their entirety. In addition to CMOS, however, biCMOS (i.e., bipolar and CMOS) processing may also be used, such as a process that would include a PMOS or NMOS FET array with bipolar structures on the periphery. Alternatively, other technologies may be employed wherein a sensing element can be made with a three-terminal devices in which a sensed ion leads to the development of a signal that controls one of the three terminals; such technologies may also include, for example, GaAs and carbon nanotube technologies.
Taking a CMOS example, a P-type ISFET fabrication is based on a P-type or N-type silicon substrate, in which an n-type well forming a transistor “body” is formed. Highly doped P-type (P+) regions S and D, constituting a source and a drain of the ISFET, are formed within the n-type well. A highly doped N-type (N+) region B may also be formed within the n-type well to provide a conductive body (or “bulk”) connection to the n-type well. An oxide layer may be disposed above the source, drain and body connection regions, through which openings are made to provide electrical connections (via electrical conductors) to these regions. A polysilicon gate may be formed above the oxide layer at a location above a region of the N-type well, between the source and the drain. Because it is disposed between the polysilicon gate and the transistor body (i.e., the N-type well), the oxide layer often is referred to as the “gate oxide.”
Taking another CMOS example, an N-type ISFET fabrication is based on a P+ wafer substrate with a P− epitaxy region of typically several microns thick, in which a P-type well creating a transistor “body” is formed. The P-type well is shared amongst all devices in the array and the P+ substrate serves as the bulk contact such that no other contacts are required at the pixel array. Highly doped N-type (N+) regions S and D, constituting a source and a drain of the ISFET, are formed within the P-type well. An oxide layer may be disposed above the source, drain and body connection regions, through which openings are made to provide electrical connections (via electrical conductors) to these regions. A polysilicon gate may be formed above the oxide layer at a location above a region of the N-type well, between the source and the drain. Because it is disposed between the polysilicon gate and the transistor body (i.e., the p-type well), the oxide layer often is referred to as the “gate oxide.”
Like a MOSFET, the operation of an ISFET is based on the modulation of charge concentration (and thus channel conductance) caused by a MOS (Metal-Oxide-Semiconductor) capacitance. This capacitance is constituted by a polysilicon gate, a gate oxide and a region of the well (e.g., N-type well) between the source and the drain. When a negative voltage is applied across the gate and source regions, a channel is created at the interface of the region and the gate oxide by depleting this area of electrons. For an N-well, the channel would be a P-channel (and vice-versa). In the case of an N-well, the P-channel would extend between the source and the drain, and electric current is conducted through the P-channel when the gate-source potential is negative enough to attract holes from the source into the channel. The gate-source potential at which the channel begins to conduct current is referred to as the transistor's threshold voltage VTH (the transistor conducts when VGS has an absolute value greater than the threshold voltage VTH). The source is so named because it is the source of the charge carriers (holes for a P-channel) that flow through the channel; similarly, the drain is where the charge carriers leave the channel.
As described in Rothberg, an ISFET may be fabricated with a floating gate structure, formed by coupling a polysilicon gate to multiple metal layers disposed within one or more additional oxide layers disposed above the gate oxide. The floating gate structure is so named because it is electrically isolated from other conductors associated with the ISFET; namely, it is sandwiched between the gate oxide and a passivation layer that is disposed over a metal layer (e.g., top metal layer) of the floating gage.
As further described in Rothberg, the ISFET passivation layer constitutes an ion-sensitive membrane that gives rise to the ion-sensitivity of the device. The presence of analytes such as ions in an analyte solution (i.e., a solution containing analytes (including ions) of interest or being tested for the presence of analytes of interest), in contact with the passivation layer, particularly in a sensitive area that may lie above the floating gate structure, alters the electrical characteristics of the ISFET so as to modulate a current flowing through the channel between the source and the drain of the ISFET. The passivation layer may comprise any one of a variety of different materials to facilitate sensitivity to particular ions; for example, passivation layers comprising silicon nitride or silicon on/nitride, as well as metal oxides such as silicon, aluminum or tantalum oxides, generally provide sensitivity to hydrogen ion concentration (pH) in an analyte solution, whereas passivation layers comprising polyvinyl chloride containing valinomycin provide sensitivity to potassium ion concentration in an analyte solution. Materials suitable for passivation layers and sensitive to other ions such as sodium, silver, iron, bromine, iodine, calcium, and nitrate, for example, are known, and passivation layers may comprise various materials (e.g., metal oxides, metal nitrides, metal oxynitrides). Regarding the chemical reactions at the analyte solution/passivation layer interface, the surface of a given material employed for the passivation layer of the ISFET may include chemical groups that may donate protons to or accept protons from the analyte solution, leaving at any given time negatively charged, positively charged, and neutral sites on the surface of the passivation layer at the interface with the analyte solution.
With respect to ion sensitivity, an electricstatic potential difference, commonly referred to as a “surface potential,” arises at the solid/liquid interface of the passivation layer and the analyte solution as a function of the ion concentration in the sensitive area due to a chemical reaction (e.g., usually involving the dissociation of oxide surface groups by the ions in the analyte solution in proximity to the sensitive area). This surface potential in turn affects the threshold voltage of the ISFET; thus, it is the threshold voltage of the ISFET that varies with changes in ion concentration in the analyte solution in proximity to the sensitive area. As described in Rothberg, since the threshold voltage VTH of the ISFET is sensitive to ion concentration, the source voltage VS provides a signal that is directly related to the ion concentration in the analyte solution in proximity to the sensitive area of the ISFET.
Arrays of chemically-sensitive FETs (“chemFETs”), or more specifically ISFETs, may be used for monitoring reactions—including, for example, nucleic acid (e.g., DNA) sequencing reactions, based on monitoring analytes present, generated or used during a reaction. More generally, arrays including large arrays of chemFETs may be employed to detect and measure static and/or dynamic amounts or concentrations of a variety of analytes (e.g., hydrogen ions, other ions, non-ionic molecules or compounds, etc.) in a variety of chemical and/or biological processes (e.g., biological or chemical reactions, cell or tissue cultures or monitoring, neural activity, nucleic acid sequencing, etc.) in which valuable information may be obtained based on such analyte measurements. Such chemFET arrays may be employed in methods that detect analytes and/or methods that monitor biological or chemical processes via changes in charge at the chemFET surface. Such use of ChemFET (or ISFET) arrays involves detection of analytes in solution and/or detection of change in charge bound to the chemFET surface (e.g. ISFET passivation layer).
Research concerning ISFET array fabrication is reported in the publications “A large transistor-based sensor array chip for direct extracellular imaging,” M. J. Milgrew, M. O. Riehle, and D. R. S. Cumming, Sensors and Actuators, B: Chemical, 111-112, (2005), pp. 347-353, and “The development of scalable sensor arrays using standard CMOS technology,” M. J. Milgrew, P. A. Hammond, and D. R. S. Cumming, Sensors and Actuators, B: Chemical, 103, (2004), pp. 37-42, which publications are incorporated herein by reference and collectively referred to hereafter as “Milgrew et al.” Descriptions of fabricating and using ChemFET or ISFET arrays for chemical detection, including detection of ions in connection with DNA sequencing, are contained in Rothberg. More specifically, Rothberg describes using a chemFET array (in particular ISFETs) for sequencing a nucleic acid involving incorporating known nucleotides into a plurality of identical nucleic acids in a reaction chamber in contact with or capacitively coupled to chemFET, wherein the nucleic acids are bound to a single bead in the reaction chamber, and detecting a signal at the chemFET, wherein detection of the signal indicates release of one or more hydrogen ions resulting from incorporation of the known nucleotide triphosphate into the synthesized nucleic acid.
A problem that exists within many of these circuits and arrays relates to tolerances in the circuit fabrication process. The same types of circuits may have somewhat different characteristics from one another because of inherent variances in the circuit components and their relative structures that occur from fabrication tolerances. These differences in circuits that are intended to be identical circuits is often referred to as a mismatch.
An example of offset and mismatch may be an amplifier mismatch that occurs in circuits due to threshold mismatch between the devices of the input differential pair that are intended to be identical. Arrays having numerous amplifiers that are intended to be identical, but are not, are typical of circuits that can exhibit mismatch. Active pixel sensors are an example of devices where this mismatch and offset may be critical. Active pixel sensors are image sensing arrays having a number of pixels, and each pixel is associated with an amplifier to output the light sensed by that pixel. A common approach to correcting for amplifier mismatch within active pixel sensors is correlated double sampling. In correlated double sampling, one sample is taken of a reset pixel value and another sample taken of the pixel with the signal from sensed light. A difference is taken between the two samples. The difference in samples should represent the actual signal free of offsets including a reduction in thermal noise if the samples are time correlated. In order to acquire the two samples, a reset value is required. Correlated double sampling can be effective in removing various types of offsets and transistor mismatch problems.
However, there are sensing arrays that have sensing elements that are continually being read over a time period may not enable reset circuits to be used within those sensing elements. Without this reset value to be sampled, correlated double sampling is not a useable technique because of the absence of a reset value or reference value that is correlated to the sensing devices. Therefore, there is a need in the prior art for providing double sampling circuits that cannot employ correlated double sampling techniques.
In addition, transistor mismatch in CMOS circuits can impose severe limitations for sensor arrays. This may be especially true for sensors with small output levels. The total deviation that inherently results during the fabrication processes creates non-uniformity in the transistors within the array of sensors resulting in signal offsets and non-uniformity within the signal created by these transistors. Therefore, it is desirable to eliminate or reduce such non-uniformity and offsets, especially before the A/D conversion. From the foregoing discussion, there remains a need within the art for a circuit that can eliminate offsets and mismatches within circuits, even those without reset capabilities.